With the exponential rise in quantity of data to manage, the modern data centre is increasingly limited by the capacity of individual machines. Since storage and compute demand more capacity than can be provided by a single machine, we distribute both over large clusters and use the network to transfer data between where it is stored and where it is processed. Moving all that data around uses deep storage stacks which incur a significant performance impact. If we could somehow flatten the storage stack and provide applications with direct access to data, then we could improve performance by orders of magnitude.
Hewlett Packard Enterprise recently demonstrated that we can do exactly with their research project, ""The Machine"". Instead of moving data around with a network, The Machine uses multi terabytes of persistent memory and a next generation fabric-attached memory interconnect to provide a single pool of storage which can be accessed by any processor in the cluster. It shows that we can provide applications with immediate load/store access to huge data sets in a model called Memory-Driven Computing.
Proof in hand, now it is time to bring Memory-Defined Computing to the data centre. Gen-Z is an open systems interconnect designed to provide memory semantic access to data and devices via direct attached, switched or fabric topologies. HPE has joined the Gen-Z consortium and is using the knowledge gained with The Machine to help shape Gen-Z to set the stage for true Memory-Driven Computing. With putting memory at the centre, this enables us to overcome the limitations of today's computing systems and power innovations.
This session will cover two topics. It will start with a status update on The Machine and an overview of how it works. Then we'll shift into an introduction of Gen-Z, and how it can reshape the architecture of computing in the years to come.
This session will cover new features and additions to QEMU that happened over the last year, ranging from new features for KVM support to Multi-Threaded TCG (MTTCG) and QEMU linux-user improvements. We will also discuss upcoming work to support LITE and IoT development and hope for a healthy discussion on requirements for members interested in these areas.
The ARM ecosystem needs full stack development tools, currently you need an Intel machine to develop for ARM. This makes developing for ARM a 2nd class citizen. The need is shown greatly in the datacenter where we need developers and engineers to start working on ARM as a 1st class citizen. To enable this developers need access to ARMv8 based development systems with UEFI and ACPI capability. From small NUC like devices (with expandable memory and SATA ssd/disk), to ARM powered notebooks and workstations (that provide PCIe, SATA and DIMM). Finally ARM server access as cloud/baremetal instances for production testing. This session is to gather requirements and review options that can be provided/developed.
On a device it’s not uncommon to share power domains between secure and non-secure side, for example between a TEE and Linux kernel. With that comes some challenges that needs to be taken care of and that is the theme for this presentation. We’ve identified a couple of challenges when it comes to power management and security. One case is when sharing power resources (clock, power domains, ...) between secure and non-secure devices. Another is to make a proper shutdown and boot-up sequence (CPU on/off etc) and finally there has been some concerns regarding the latency when communicating with PSCI. In this session we would like to highlight those and discuss what the short and long term plans are.
The University of Sao Paulo, with support of LSITEC (an NGO Design House), has all of the necessary equipment to design and manufacture 96boards computers and mezzanine boards. Working with one of Linaro’s partners, LeMaker, LSITEC has produced the LeMaker Guitar single board computer under license, and is now looking forward to producing 96boards and accessories the same way. The final goal is to strengthen the gap between industry and universities, producing professionals with high design skills in embedding computing to society, while providing to Linaro and its partners the ability to have high quality boards in various volumes of manufacturing.
GPGPUs (General Purpose Graphics Processing Unit) are becoming a relevant functional block on SoCs, particularly on the ARM ecosystem. Extracting full performance of a GPU is now becoming a combination of well integrated and optimized software and hardware. Motivated by that, there are many Open GPU initiatives around the world using FPGAs, but most (if not all) of these are on Intel platforms. This project aims to present an Open GPU based on an FPGA using the ARM Instruction Set. The driver platform adopted was the well know MESA 3D (www.mesa3d.org). We will describe the co-design approach to designing the OpenGPU. A functional demonstration of the OpenGPU working on a range of OpenGl applications ported by Linaro will be shown. On the fly we will change drivers between: SW only, GPU on Asic, and OpenGPU to see its performance impact. The engineers that implemented this system will be at the session to support detailed technical questions.