This session is meant to look at Coresight in deeper details. The goal is to go ove more advanced concepts that are going beyond the basic traces mechanism such as STMs and how it could be used to interleave messages from the existing kernel trace infrastructure with the Coresight trace stream. The second part will concentrated on some of the challenges we face such as the configuration of STM trace channels between user and kernel space, the representation of metadata
for trace decoding and the decoding of compressed streams themselves. The presentation will conclude with a use case example and it's associated decoded trace stream.
This session will be a presentation about currently available binary analysis tools, including: Sanitizers, perf (a performance counter and tracing profiling tool), record/replay (a reverse debugging facility in GDB) and prelink rootfs.
QEMU ARMv8-A system emulation was completed shortly after LCA14 and has been fully upstreamed in QEMU. During this session we will briefly cover the level of support and functionality, and we will introduce developers to using QEMU for running 64-bit ARM kernels and distributions using QEMU. We also developed a small set of patches on top of upstream QEMU which allows us to run a 64-bit Android build. We will explain the status and efforts coordinated between Google and Linaro, demo the working system, and show how developers can start playing with this.
Several engineers from ARM and Linaro attended the EAS workshop at Kernel Summit. The goal of the session is to update everyone else on the key outcomes of the workshop and outline the plan going forward.
Task scheduling on big.Little targets is a known challenge in the community. A commercial grade solution exists with ARM's Global Task Scheduler and there is a second solution being developed by ARM to solve this problem in a more generic, upstream-friendly way. The HMP scheduler extensions developed at Qualcomm Innovation Center (QuIC) were created to achieve many of the same benefits being sought in the power-aware scheduler in current development upstream, along with perhaps some additional ones. This presentation will cover the features, design and status of QuIC's HMP scheduler extensions.
Some areas of interest from ARM-Linaro perspective:
- Some intro to their target arch/platform.
- Architecture of their software solution (sched, load tracking algorithm, power- management from the scheduler, energy model description and use, DT etc).
- Pain points from an upstream integration PoV.
- Results, if any.