Designing SoCs with multiple cores improves the overall performance of the system but it comes with higher cost of implementation. A solution to address this problem is to connect two or more SoCs over a cache coherent link such that the number of cores in the overall system is multiplied by ‘n’ times if ‘n’ SoCs are interconnected. OS running on this linked-system uses the total amount of resources (cores and memory) from all the SoCs. Individual SoC’s resources can be separated in different NUMA nodes for efficient scheduling of tasks.
This session covers how CCIX (Cache Coherent Interconnect for Accelerators) protocol acting over standard PCIe transport caters for SMP Linux boot on a multi-socket SoC implementation.
It will also provide implementation information on N1SDP (Neoverse N1 System Development Platform) where two N1SDP SoCs are connected over a CCIX link.
(“N1SDP is a test chip platform developed by ARM and aimed at realizing the high performance, scalable solution for the infrastructure workloads from cloud to edge.”)
Manoj Kumar Eswaramoorthi
Senior Platform Firmware Engineer (ARM)
Manoj is a Senior platform firmware engineer in ARM's OSS platform software group focusing on bring up and reference software stack development for test chips and reference platforms.