System Device Tree is an ongoing effort to expand the scope of Device Tree to describe and configure modern heterogeneous SoCs, including multiple CPUs clusters, their views of the system, and the software running on them. System Device Tree comes with Lopper, an Open Source Python tool to read a System Device Tree and produce one traditional Device Tree for each software execution domain.
The System Device Tree specification progressed significantly in the last year. This presentation will provide an update on the latest developments, such as the new bindings for the description and configuration of bus firewalls. The talk will deep-dive into Lopper, its flexible plugins architecture, and explain how to use it with System Device Tree today. If time allows, some common System Device Tree and Lopper use cases will be demonstrated.
CTO Open Source (Xilinx)
Tomas Evensen is Chief Technology Officer, Open Source at Xilinx.<br>In this role he is responsible for the open source software strategy for<br>Xilinx All Programmable SoCs. Prior to joining Xilinx, Evensen was Chief<br>Technology Officer at Wind River for 7 years, as well as GM for the Wind<br>River Tools Division and VP of Engineering for the VxWorks operating system.<br>Before that he was the creator of the Diab Data C/C++ compilers.<br>Evensen received his MSEE at the Royal Institute of Technology in Stockholm, Sweden.
Principal Engineer (Xilinx)
Stefano Stabellini serves as system software architect and virtualization lead at Xilinx, the world's largest supplier of FPGA solutions. Previously, at Aporeto, he created a virtualization-based security solution for containers and authored several security articles. As Senior Principal Software Engineer in Citrix, he led a small group of passionate engineers working on Open Source projects. Stefano has been involved in Xen development since 2007. He created libxenlight in November 2009 and started the Xen port to ARM with virtualization extensions in 2011. Today he is a Xen Project committer, and he maintains Xen on ARM and Xen support in Linux and QEMU.
Principal Engineer (Xilinx)
Bruce Ashfield is currently a system software architect and Yocto technical lead at Xilinx, the worlds largest supplier of FPGA solutions. Previously, at Wind River, he created a embedded products based on the Yocto project. Bruce had a particular focus in virtualization and cloud native solutions, creating both a real time virtualization profile (Open Virtualization Profile) and a container based edge OS (OverC). Bruce continues as the kernel, meta-virtualization, meta-realtime and container maintainer for the Yocto project as well as working on System Device tree (among other things) at Xilinx.