LVC21-219: Enabling Collaborative Processor Performance Control (CPPC) on Arm Platforms

Session Abstract

Collaborative Processor Performance Control (CPPC) defined in the ACPI spec describes a mechanism for the OS to manage the performance of the processor core on a contiguous and abstract performance scale. This talk focuses on enabling CPPC support on Arm architecture based platforms that support architected Activity Monitor Unit (AMU). Key takeaways for audience include introduction of SCMI Fastchannels, AMU counters, AMU interfaced as a Function Fixed Hardware (FFH), using fastchannel as the communication medium with platform firmware for requesting desired performance and using the AMU counter values to calculate the CPU operating frequency. An implementation of CPPC allows OS to request the firmware for the desired performance level and allows monitoring of the CPU performance. The OS request to firmware involves the use of non-secure SCMI FastChannel (a memory mapped channel between the OS and platform firmware). The monitoring of the CPU performance involves the use of architected AMU counters (the CPU frequency counter and the constant frequency counter of the AMU). This session discuss all the aspects related to enabling CPPC support on an Arm platform and uses Arm’s Neoverse Reference Design (RD) platform as an example.

Session Speakers

Pranav Madhu

Arm (Software Engineer)

Pranav is a Software Engineer in the Open Source Software group at Arm. He works on platform software development for Arm's Neoverse enterprise reference platforms. His main focus has been on ServerReady compliance and enabling power management functionality for Neoverse platforms.

Collaborative Processor Performance Control (CPPC) defined in the ACPI spec describes a mechanism for the OS to manage the performance of the processor core on a contiguous and abstract performance scale.

This talk focuses on enabling CPPC support on Arm architecture based platforms that support architected Activity Monitor Unit (AMU). Key takeaways for audience include introduction of SCMI Fastchannels, AMU counters, AMU interfaced as a Function Fixed Hardware (FFH), using fastchannel as the communication medium with platform firmware for requesting desired performance and using the AMU counter values to calculate the CPU operating frequency. An implementation of CPPC allows OS to request the firmware for the desired performance level and allows monitoring of the CPU performance. The OS request to firmware involves the use of non-secure SCMI FastChannel (a memory mapped channel between the OS and platform firmware). The monitoring of the CPU performance involves the use of architected AMU counters (the CPU frequency counter and the constant frequency counter of the AMU).

This session discuss all the aspects related to enabling CPPC support on an Arm platform and uses Arm’s Neoverse Reference Design (RD) platform as an example.

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