The challenge of SVE in QEMU - SFO17-103

Session ID: SFO17-103 Session Name: The challenge of SVE in QEMU - SFO17-103 Speaker: Alex Bennée Track: Virtualization

★ Session Summary ★ Arm’s Scalable Vector Extensions present an innovative way of scaling silicon performance without needing to constantly re-write your code. However for a system emulator like QEMU it presents a number of challenges. There are fairly routine problems like implementing the necessary architecture pre-requisites of half-precision and complex numbers. There are more complex interactions where our recent work on multi-threaded execution interacts with the need to support SVE’s memory model and atomicity requirements. Also making increasing use of SIMD instructions also hits one of QEMUs performance bottle-necks as the implementation of multiple-vector operations are several times slower than “normal” scalar integer instructions. As we also take instruction verification seriously we need to look at improving our testing tools that currently have naive assumptions about results of an individual instruction across various implementations. As you will see implementing SVE is more than just adding a few extra instructions. ————————————————— ★ Resources ★ Event Page: Presentation: Video: —————————————————

★ Event Details ★ Linaro Connect San Francisco 2017 (SFO17) 25-29 September 2017 Hyatt Regency San Francisco Airport

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Event Date: 25 Sept 2017

Speakers: Alex Bennée

Position: Senior Engineer at Linaro

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