A flow aware scheduler is introduced based on application requirements to support millions of flows. This feature will provide the ability for applications to create flows on the fly without any HW constraints. The flows are light-weight queues and packets can be enqueued into a queue with a specific flow id. This enables the application to have dynamic flow handling required for better synchronization. ODP now provides APIs to support this type of lightweight flow processing that can leverage hardware acceleration designed to assist such dynamic flow processing. This talk discusses the types of ordered flows typically found in network packet processing applications and the mechanisms that are needed to process them efficiently on modern network SoCs.
YVR18-217:Lightweight flows for fine-grain packet order processing
Supporting Complex MIPI DSI Bridges in a Linux systemFriday, September 24, 2021
Display interface solutions are often critical to design due a mismatch between System On Chips(SoC) and it’s associated application-specific display devices. A display interface bridge prevents this mismatch by converting...
HKG18-HK16 - PMWG Hacking: Big/Little Capacity AwarenessWednesday, April 11, 2018
Session ID: HKG18-HK16 Session Name: HKG18-HK16 - PMWG Hacking: Big/Little Capacity Awareness Speaker: Vincent Guittot Track: Power Management ## Session Summary ## big/LITTLE capacity awareness ## Resources Event Page: http://connect.linaro.org/resource/hkg18/hkg18-hk16/...
SAN19-106 - What’s new in VIXL 2019?Friday, October 4, 2019
VIXL is a ARMv8 Runtime Code Generation Library which contains three components:
- Programmatic assemblers to generate A64, A32 or T32 code at runtime.
- Disassemblers that can print any instruction emitted by the assemblers.
- Simulator can simulate any instruction emitted by the A64 assembler on x86 and ARM platform. It is configurable, vector length for SVE, for example, and it supports register tracing during the execution.
In this talk, were going to introduce:
- What is VIXL? It is already deployed and is considered “mature”, for example, it has been adopted by Android ART compiler for its ARM backends: AArch64 and AArch32.
- CPU feature management and detection.
- New Armv8.x instructions support, e.g. BTI, PAuth, etc.
- New SVE (Scalable Vector Extension) support.
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