YVR18-303:Managing customized FPGA accelerators with SDSoC!

Using Xilinx SDSoC and HLS as a model, this presentation, will discuss the merits and abilities of customized hardware accelerators involved with performance aspects of embedded systems. Using a designed and tested accelerator on the Avnet Ultra96, performance, power, development time metrics will be compared. Through comparing these various metrics, a new path forward for hardware accelerated software designs will be shown as a path forward for the embedded space. While this is a presentation, the author welcomes discussion!

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