The Python community can strongly benefit from the immense and flexible computing power of Field Programmable Gate Arrays (FPGA). FPGAs are composed of memories, various logic and math hardware units that can be programmed and configured to accelerate any algorithm. They can be used to even create your own custom CPUs and other gadgets. FPGA chips have presently evolved into multi-faceted Systems on a Chip (SoC) which include multi-core CPUs and hardware accelerators such as embedded GPUs, video codecs, FEC and hardware interfaces such as USB. These FPGA SoCs are similar to other SoCs such as Raspberry Pi or Beaglebone boards but those lack the power of the FPGA. With the right system design the FPGA can turn them into super turbo charged machines. Many SoCs with FPGAs run full Arm Linux and can utilize popular package manager root file systems (Debian, Ubuntu, etc) as well as support for the full Python 2x and 3x environments. FPGA SoCs are being positioned to take over the edge, cloud and machine learning realms by some of the top vendors in the computing industry. What is missing is a clean cohesive means to interface Python code to harness the acceleration that the FPGA hardware can provide. This talk will outline the current state of development tools and methods for the new Ultra96 board that Avnet and Xilinx have just released. The intent is to show the community the value of the proposition and implore them to work together to achieve a more homogeneous and simplified approach to taking Python to the next level.
YVR18-311:A Call to Action: Accelerating Python with FPGAs
LVC21F-321 The LLVM Embedded Toolchain for Arm, a new open source toolchainTuesday, August 24, 2021
Level: Intermediate For many years the GNU Arm Embedded Toolchain has provided an open-source toolchain targeting embedded systems. The LLVM Embedded Toolchain for Arm is a new open-source project with the goal of providing an LLVM based equivalent to the GNU Embedded toolchain. We would like the LLVM Embedded Toolchain to lower the bar to entry of using LLVM in Embedded systems. Initially targeting M profile systems with a special focus on v8.1-M. The presentation will contain a description of: * Why do we need an LLVM Embedded Toolchain for Arm? * The challenges of targeting embedded systems with LLVM components and how the LLVM Embedded Toolchain addresses them. * A comparison between the LLVM Embedded Toolchain for Arm and the GNU Arm Embedded Toolchain. * Future plans. The project is hosted at https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm with build scripts under an Apache License.
LVC21F-319 TVM for micro targetsTuesday, August 24, 2021
Level: Intermediate TVM is an open source machine learning framework for CPU, GPUs, microcontrollers, and various hw accelerators. It basically takes a given ML model as input (it accepts various standard formats, like ONNX, TFlite, and Keras) and generates optimized native code for a given HW target, allowing one to run the input model fast on the specified device/target. In the last LVC2021 at the beginning of this year we've presented the work we had done regarding enabling microTVM (TVM's component used to run TVM on micro targets - i.e. boards running m-series Arm CPUs and other microcontrollers) and TVM CI to support new micro targets, . Hence, in this presentation we would like to show the advances since the last report, particularly about the microTVM support for new micro targets and also about new features added to the TVMC (TVM's cli) to ease working with micro targets. For TVMC we'll present the new 'micro' context which allows one to easily compile a Neural Network, build an image to be flashed to the micro target, flash the image built, and finally run the model in the micro target. To illustrate that new workflow it will be demonstrated how to run a simple NN model on a real (physical) ST dev board using the 'tvmc' cli.
LVC21F-318 Testing TensorFlow AARCH64 packagesTuesday, August 24, 2021
Level: Advanced The journey to having an automated and robust process to provide a consistent means of ensuring that the AARCH64 builds of TensorFlow packages meet an acceptable level of operation. Will also include a survey of the current state of the main ML frameworks.
Handing the Emperor a towel: automating license compliance information - SFO17-311Monday, September 25, 2017
Session ID: SFO17-311 Session Name: Handing the Emperor a towel: automating license compliance information - SFO17-311 Speaker: Kate Stewart Track: ★ Session Summary ★ For many years, companies have known...
YVR18-315:How to build affordable panoramic Camera product with Bubblegum96Sunday, September 16, 2018
Bubblegum-96 with Actions S900 SoC inside, connected with 2 lanes of MIPI-CSI fisheye cameras, was used in this case, to build affordable panoramic camera. With special algorithm and GPU acceleration,...
Panel: Arm in open source (David Rusling) - SFO17-500K2Friday, October 6, 2017
Session ID: SFO17-500K2 Session Name: Panel: Arm in open source (David Rusling) - SFO17-500K2 Speaker: David Rusling Track: ★ Session Summary ★ --------------------------------------------------- ★ Resources ★ Event Page: http://connect.linaro.org/resource/sfo17/sfo17-500k2/ Presentation:...
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